In the manufacture of semiconductor devices such as transistors on a substrate such as a silicon wafer, silicon lines are needed to form the transistor gates. Silicon gates are made by depositing a polysilicon layer over a dielectric silicon oxide layer (the gate oxide). An additional metal silicide layer may also be added to reduce the resistivity of the interconnect. These layers are then etched so as to leave conductive polysilicon or polycide lines on the silicon oxide dielectric.
Many important device performance parameters are sensitive functions of transistor channel length for smaller devices. As a consequence, the physical dimensions of the etched polysilicon and polycide lines are critical, as the channel length of the transistors depends on the width of these lines. In order to maintain high device yield, precise control of the polysilicon and polycide linewidth is required. This control can be achieved by maintaining vertical sidewall profiles (anisotropic profiles) for all etched lines on the substrate, regardless of position or local environment (low profile microloading). An additional strict requirement is imposed by the gate oxide layer. To achieve high device densities while maintaining necessary electrical characteristics, thinner gate oxides are required. As a consequence of the reduced thickness, high selectivity of silicon to silicon oxide is required by the etch process to avoid erosion of the gate oxide layer. Generally the polysilicon and polycide lines have been etched in a plasma of a halogen gas, such as a chlorine-containing gas, a fluorine-containing gas, a bromine-containing gas, or mixtures of halogen-containing gases. Plasma etching can produce anisotropic profiles while maintaining high selectivity, and plasma etching of silicon-containing materials is now widely used.
Conventional plasma etch processes however have several problems; some isotropic etching takes place, causing an inward bowing of the lines, causing negatively sloped, or re-entrant sidewalls, and causing notching at the interfaces between the silicide and polysilicon layers as well as between the polysilicon lines and the silicon oxide layer.
When the polysilicon lines are required to be less than one-half micron in width, high density plasmas with independent plasma generation and ion energy control have been used. These etchers generally operate under high ion current and low ion energy conditions. The pressure in these chambers is also lower than conventional etching, in the range of 1 to 50 millitorr. These conditions, while producing vertical profiles, high selectivity and low profile microloading, result in reduced passivation of the polysilicon and/or polycide sidewalls during the entire etch process. The reduced passivation can lead to the undesirable sidewall features including linewidth loss, bowing and notching.
After a polysilicon or polycide line has been etched down to the silicon oxide layer, which is known as the main etch step, i.e., the etch endpoint has been reached, an overetch step is performed to remove any remaining silicon material on the exposed silicon oxide substrate. This overetch step is used to remove "stringers" and other silicon-containing material still remaining. The overetch is even more sensitive to sidewall attack than the main etch. During the main etch, the silicon-containing reaction byproducts of the polysilicon and silicon oxide removal may deposit on the polysilicon/polycide sidewalls to provide protection from lateral (isotropic) etching. Since the overetch conditions are chosen so that selectivity between the silicon-containing material being etched and the underlying layer material is high, and only the stringers remain from the initial layer, very little silicon-containing material is being removed during the overetch step, and the protective reaction by-products that deposited on the sidewalls during the main etch step are being formed only in very small amounts. Thus very little sidewall protection is available during the overetch step, with the result that lateral etching occurs. This lateral etching results in unsatisfactory profiles, including bowing, notching and line width loss. Such a sidewall is seen in FIG. 1, wherein the problems are seen slightly exaggerated. As shown in FIG. 1A, in a typical etched polysilicon line 12, there is a notch 14 at the interface between the polysilicon layer 12 and the substrate 16. As shown in FIG. 1B, bowing of the polysilicon sidewall is shown at 18. FIG. 1C illustrates linewidth loss at 20.
When the polysilicon line 12 is to be encapsulated, e.g., with a dielectric such as silicon oxide or silicon nitride, voids will be formed at the notch 14, and along the bowed sidewall 18. In addition, precise control of the linewidth is not possible because of the lateral etching.
Thus the search for an improved process that provides improved protection of the sidewall during etching, during both the main etch and the overetch, to produce straight sidewalls and eliminate notching has continued.